Imaging systems and methods for performing column-based image sensor pixel gain adjustments

ABSTRACT

An imaging system may include an array of image pixels arranged in rows and columns that includes first and second pixels in two different columns and a common row. A first column readout circuit may control the first pixel to exhibit a first gain and a second column readout circuit may control the second pixel to exhibit a second gain. The first and second readout circuits may determine whether to adjust the gain of the first and second pixels based on image signals that are captured by the first and second pixels. For example, the first readout circuit may selectively activate a dual conversion gain transistor in the first pixel based on an image signal received from the first pixel and the second readout circuit may independently and selectively activate a dual conversion gain transistor in the second pixel based on an image signal received from the second pixel.

This application claims the benefit of provisional patent applicationNo. 61/869,433, filed Aug. 23, 2013, which is hereby incorporated byreference herein in its entirety.

BACKGROUND

This relates generally to imaging devices, and more particularly, toimaging devices having pixel arrays with per-pixel gain adjustmentcapabilities.

Image sensors are commonly used in electronic devices such as cellulartelephones, cameras, and computers to capture images. In a typicalarrangement, an electronic device is provided with an array of imagepixels arranged in pixel rows and pixel columns. Row control circuitryis coupled to each pixel row over row control lines for providing pixelcontrol signals to each image pixel in the pixel row. Image pixels areoften operated in a low gain mode for capturing images of brighterscenery and in a high gain mode for capturing images of darker scenery.

In conventional imaging systems, row control circuitry provides controlsignals to each pixel in a selected pixel row that instruct every pixelin that row to operate in either the high gain mode or the low gainmode. However, scenes to be imaged often include both brighter anddarker portions across any given row of image pixels. Performing imagecapture operations using conventional image sensors that control imagepixels in an entire pixel row to operate in the high gain or low gainmode may thereby cause some image pixels in a given pixel row togenerate excessively noisy or over-saturated image signals, which cangenerate unsightly image artifacts in the final captured image.

It would therefore be desirable to be able to provide imaging deviceswith improved means of capturing and processing image signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an illustrative imaging system having an imagesensor and processing circuitry for capturing images using column-basedpixel gain adjustments in accordance with an embodiment of the presentinvention.

FIG. 2 is a diagram of an illustrative pixel array and associatedper-column control and readout circuits for controlling gain adjustmentsin pixels of corresponding pixel columns in accordance with anembodiment of the present invention.

FIG. 3 is a circuit diagram of illustrative image sensor pixels in twocolumns and two rows of a pixel array that are coupled to respectivecolumn control and readout circuits for independently capturing andoutputting image signals using selected pixel gains in accordance withan embodiment of the present invention.

FIG. 4 is a flow chart of illustrative steps that may be performed by aper-column control and readout circuit for adjusting the conversion gainof a corresponding pixel in response to image signals captured by thatpixel in accordance with an embodiment of the present invention.

FIG. 5 is a flow chart of illustrative steps that may be performed by aper-column control and readout circuit for adjusting the conversion gainof a corresponding pixel and adjusting the gain of a column readoutamplifier coupled to the pixel in response to image signals captured bythat pixel in accordance with an embodiment of the present invention.

FIG. 6 is an illustrative timing diagram showing how a per-columncontrol and readout circuit may turn on a dual conversion gain gate in acorresponding pixel while row control circuitry continuously asserts arow select signal to a row select gate in the pixel for adjusting theconversion gain of the pixel in response to image signals captured bythat pixel in accordance with an embodiment of the present invention.

FIG. 7 is a block diagram of a processor system employing theembodiments of FIGS. 1-6 in accordance with an embodiment of the presentinvention.

DETAILED DESCRIPTION

Electronic devices such as digital cameras, computers, cellulartelephones, and other electronic devices may include image sensors thatgather incoming light to capture an image. The image sensors may includearrays of image pixels. The pixels in the image sensors may includephotosensitive elements such as photodiodes that convert the incominglight into image signals. Image sensors may have any number of pixels(e.g., hundreds or thousands or more). A typical image sensor may, forexample, have hundreds of thousands or millions of pixels (e.g.,megapixels). Image sensors may include control circuitry such ascircuitry for operating the image pixels and readout circuitry forreading out image signals corresponding to the electric charge generatedby the photosensitive elements.

FIG. 1 is a diagram of an illustrative imaging system such as anelectronic device that uses an image sensor to capture images.Electronic device 10 of FIG. 1 may be a portable electronic device suchas a camera, a cellular telephone, a tablet computer, a webcam, a videocamera, a video surveillance system, an automotive imaging system, avideo gaming system with imaging capabilities, or any other desiredimaging system or device that captures digital image data. Camera module12 may be used to convert incoming light into digital image data. Cameramodule 12 may include one or more lenses 14 and one or morecorresponding image sensors 16. Lenses 14 may include fixed and/oradjustable lenses and may include microlenses formed on an imagingsurface of image sensor 16. During image capture operations, light froma scene may be focused onto image sensor 16 by lenses 14. Image sensor16 may include circuitry for converting analog pixel data intocorresponding digital image data to be provided to storage andprocessing circuitry 18. If desired, camera module 12 may be providedwith an array of lenses 14 and an array of corresponding image sensors16.

Storage and processing circuitry 18 may include one or more integratedcircuits (e.g., image processing circuits, microprocessors, storagedevices such as random-access memory and non-volatile memory, etc.) andmay be implemented using components that are separate from camera module12 and/or that form part of camera module 12 (e.g., circuits that formpart of an integrated circuit that includes image sensors 16 or anintegrated circuit within module 12 that is associated with imagesensors 16). Image data that has been captured by camera module 12 maybe processed and stored using processing circuitry 18 (e.g., using animage processing engine on processing circuitry 18, using an imagingmode selection engine on processing circuitry 18, etc.). Processed imagedata may, if desired, be provided to external equipment (e.g., acomputer, external display, or other device) using wired and/or wirelesscommunications paths coupled to processing circuitry 18.

As shown in FIG. 2, image sensor 16 may include a pixel array 20containing image sensor pixels 22 arranged in rows and columns(sometimes referred to herein as image pixels or pixels arranged inpixel rows and pixel columns) and control and processing circuitry 24.Array 20 may contain, for example, hundreds or thousands of rows andcolumns of image sensor pixels 22. Control circuitry 24 may be coupledto row control circuitry 26 and image readout circuitry 28 (sometimesreferred to as column control circuitry, readout circuitry, processingcircuitry, column decoder circuitry, or column control and readoutcircuitry). Row control circuitry 26 may receive row addresses fromcontrol circuitry 24 and supply corresponding row control signals suchas reset, row select, charge transfer, and readout control signals topixels 22 over row control paths 30. One or more conductive lines suchas column lines 32 (e.g., column lines 32A and 32B) may be coupled toeach column of pixels 22 in array 20. Column lines 32A may be used forreading out image signals from pixels 22, for supplying bias signals(e.g., bias currents or bias voltages), whereas column lines 32B may beused for supplying column-based pixel control signals to pixels 22. Ifdesired, during pixel readout operations, a pixel row in array 20 may beselected using row control circuitry 26 and image signals generated byimage pixels 22 in that pixel row can be read out along column lines32A. Column lines 32A and 32B may sometimes be referred to hereincollectively as conductive column lines (or column paths) each coupledto a corresponding column of array 20 (e.g., control signals may beprovided to a first column of array 20 via a first column path, signalsmay be read out from the first column along the first column path, andthat column path may include any desired number of conductive lines suchas conductive lines 32A and 32B, etc.).

Amplifier circuitry 33 may be interposed on column lines 32A (e.g., eachcolumn line 32A may have a corresponding amplifier circuit). Amplifiercircuitry 33 may amplify image signals received from an associatedcolumn of pixel array 20 and may provide the amplified image signals tocolumn control and readout circuitry 28. Amplifier circuitry 33 mayprovide received image signals with a desired gain (e.g., an adjustablegain). For example, amplifier circuitry may provide image signalsreceived from pixels 22 with a relatively high gain (e.g., when thecorresponding pixel captures darker portions of a scene) or may provideimage signals with a relatively low gain (e.g., when the correspondingpixel captures brighter portions of a scene). Column control and readoutcircuitry 28 may provide control signals to amplifier circuitry 33 andto gain circuitry in pixel 22 (e.g., over column lines 32B or otherdesired control paths) to control the gain provided by pixel 22 andamplifier circuitry 33 to the received image signals.

Image readout circuitry 28 may receive image signals (e.g., analog pixelvalues generated by pixels 22) over column lines 32A. Image readoutcircuitry 28 may include sample-and-hold circuitry for sampling andtemporarily storing image signals read out from array 20, amplifiercircuitry, analog-to-digital conversion (ADC) circuitry, bias circuitry,comparator circuitry, column memory, latch circuitry for selectivelyenabling or disabling the column circuitry, or other circuitry that iscoupled to one or more columns of pixels in array 20 for operatingpixels 22 and for reading out image signals from pixels 22. ADCcircuitry in readout circuitry 28 may convert analog pixel valuesreceived from array 20 into corresponding digital pixel values(sometimes referred to as digital image data or digital pixel data).Image readout circuitry 28 may supply digital pixel data to control andprocessing circuitry 24 and/or processor 18 (FIG. 1) over path 25 forpixels in one or more pixel columns.

Image pixels 22 may be operated in a low gain mode for capturing imagesof brighter scenery and in a high gain mode for capturing images ofdarker scenery. During image capture operations, portions of array 20may capture image signals from darker portions of an imaged scenewhereas other portions of array 20 may capture image signals frombrighter portions of the imaged scene. In the example of FIG. 2, pixels22 in portions 25 of array 20 may capture brighter portions of theimaged scene whereas pixels 22 in portions 27 may capture darkerportions of the imaged scene. If desired, different pixels 22 in a givenpixel row may be provided with respective control signals viacorresponding control lines 32B that instruct the pixels to operate witha desired gain (e.g., in either a high or low gain mode). For example,pixels 22 located in brighter region 25 of a given row of array 20 maybe provided with control signals via control lines 32B that instructthose pixels to operate in a low gain mode (e.g., to preventover-saturation of the image pixels), whereas pixels 22 located indarker region 25 of the given row of array 20 may be provided withcontrol signals via control lines 32B that instruct those pixels tooperate in a high gain mode (e.g., to improve signal-to-noise ratio inthe image signals captured by those pixels).

If desired, column readout and control circuitry 28 may includeper-column control circuits 31 that are each coupled to a respectivecolumn path 32 (e.g., to a corresponding pair of conductive column lines32A and 32B). Column control circuits 31 may include readout circuitry(e.g., sample and hold circuitry, converter circuitry, etc.) for readingout signals from the corresponding column of pixels 22 and may includecontrol circuitry for providing control circuitry to the correspondingcolumn of pixels 22 (e.g., a given column control circuit 31 may onlyreadout and provide control signals to pixels in a corresponding columnwithout reading out or controlling pixels in other columns of array 20).Control circuits 31 may provide respective control signals to thecorresponding column of pixels 22 that instruct the pixels in thatcolumn to operate with a desired gain. For example, a first controlcircuit 31 coupled to a first column line 32B may instruct pixels 22 ina first column of a selected row of array 20 to capture signals in a lowgain mode whereas a second control circuit 31 coupled to a second columnline 32B may instruct pixels 22 in a second column of the selected rowof array 20 to capture signals in a high gain mode. Control circuits 31may control the gain of a given column of pixels 22 by, for example,adjusting the gain provided by the amplifier circuit 33 in that columnand/or by adjusting gain control signals provided to the pixels 22 overlines 32B. Gain control signals provided to pixels 22 over lines 32B mayinclude, for example, dual conversion gain (DCG) control signals thatare configured to adjust the charge storage capacity of a given pixel22.

Per-column control circuits 31 may each include image signal processingcircuitry that processes signals that are read out from thecorresponding column of pixels 22. Processing circuitry in columncontrol circuits 31 may include analog comparator circuitry, digitalcomparison logic circuitry, or other processing circuitry for processingimage signals. Image processing circuitry in per-column control circuits31 may process signals read out from pixels 22 to determine whether thegain used by pixels 22 in the corresponding column needs to be adjusted.If circuit 31 determines that the gain needs to be adjusted, circuit 31may provide control signals to pixels 22 in the corresponding columnthat adjust the gain used by the pixel to capture image signals. In thisway, gain selection and adjustments used by pixels 22 for capturingimage signals may be actively adjusted for each pixel 22 across a givenrow of pixel array 20, allowing for a single row to capture signalsusing both low gain and high gain modes (e.g., based on whether certainpixels in that row are located in bright portions 25 or dark portions 27of the imaged scene).

FIG. 3 is a circuit diagram of illustrative image sensor pixels 22 thatare coupled to per-column control circuits 31 for performing per-columngain adjustment operations. As shown in FIG. 3, pixel array 20 mayinclude a first image pixel 22-1 and a second image pixel 22-2. Firstpixel 22-1 may be coupled to a first column control circuit 31-1 inreadout circuitry 28 via first column path 32-1 (including correspondingcolumn conductive lines 32A and 32B) whereas second pixel 22-2 may becoupled to a second column control circuit 31-2 in readout circuitry 28via second column lines 32-2. Amplifiers 33 are not shown in the exampleof FIG. 3 for the sake of clarity. Pixels 22-1 and 22-2 may include anydesired number of photosensitive regions for capturing image charge. Inthe example of FIG. 3, pixels 22-1 and 22-2 each include twophotosensitive regions (photodiodes) 34 coupled to a shared chargestorage node 54 (e.g., photodiodes 34 may pass captured charge to thecorresponding photodiode 54 via respective charge transfer gates 52).Each photodiode may be provided with a corresponding color filterelement 38 for capturing light of a desired color. In the example ofFIG. 3, red, green, and blue color filter elements 38 are formed overphotodiodes 34 but, in general, any desired color filter elements may beused (e.g., clear color filter elements, yellow color filter elements,infrared color filter elements, etc.). Pixels 22-1 and 22-2 may, forexample, be formed in a common row of pixel array 20. Pixels 22-1 and22-2 may receive row control signals (e.g., reset control signals RST,charge transfer control signals TXA and TXB, and row select controlsignals RS) from row control circuitry 26 via row control lines 30.

A positive power supply voltage (e.g., voltage Vaa or anotherreset-level voltage) may be supplied at positive power supply terminals39 (e.g., from column control circuits 31 or other power supplycircuitry). A ground power supply voltage (e.g., Vss) may be supplied atground terminals 48. Incoming light may be collected by photodiodes 34after passing through corresponding color filter elements 38.Photodiodes 34 convert the incoming light that passes through thecorresponding color filter element into electrical charge.

If desired, row control circuitry 26 (as shown in FIG. 2) may assertreset control signal RST before an image is acquired. This turns onreset transistors 50 (e.g., a first reset transistor 50-1 in pixel 22-1and a second reset transistor 50-2 in pixel 22-2) and resets chargestorage nodes 54 (a first charge storage node 54-1 in pixel 22-1 and asecond charge storage node 54-2 in pixel 22-2) to Vaa or anotherreset-level voltage. Charge storage nodes 54 may sometimes be referredto herein as floating diffusion nodes FD or floating diffusion regionsFD. Each charge storage node 54 may be shared by the photosensitiveregions 34 in the corresponding pixel and may store charge generated byeach photosensitive region 34 in that pixel 22. In the example of FIG.3, charge storage node 54-1 may store charge generated by photodiodes34-1 and 34-3 whereas charge storage node 54-2 may store chargegenerated by photodiodes 34-2 and 34-4. Charge storage nodes 54 may beimplemented using a region of doped semiconductor (e.g., a doped siliconregion formed in a silicon substrate by ion implantation, impuritydiffusion, or other doping techniques). The doped semiconductor region(i.e., the floating diffusion FD) exhibits a capacitance that can beused to store the charge that has been transferred from photodiodes 34(e.g., regions 54 may have a corresponding charge capacity indicative ofthe amount of charge that can be stored at region 54). The signalassociated with the stored charge on node 54 is conveyed to row selecttransistors 56 by source-follower transistors 58.

Each photodiode 34 in pixels 22 may be coupled to charge storage regions54 through a corresponding charge transfer gate 52 (e.g., a first chargetransfer gate 52-1 may be coupled between photodiode 34-1 and node 54-1in pixel 22-1, a second charge transfer gate 52-2 may be coupled betweenphotodiode 34-2 and node 54-2 in pixel 22-2, a third charge transfergate 52-3 may be coupled between photodiode 34-3 and node 54-3 in pixel22-1, etc.). Row control circuitry 26 may provide corresponding chargetransfer control signals TX to the gate terminal of each charge transfergate 52.

The reset control signal RST may be deasserted to turn off resettransistor 50 across the row of array 20. After the reset process iscomplete, transfer gate control signals TX may be asserted to turn oncorresponding transfer gates 52. When transfer transistors 52 are turnedon, the charge that has been generated by the corresponding photodiode34 in response to incoming light is transferred to charge storage node54. When it is desired to read out the value of the stored charge (i.e.,the value of the stored charge that is represented by the signal at thesource S of transistor 58), row select control signal RS may be asserted(e.g., concurrently for all pixels in the selected row). When signal RSis asserted, transistors 56 turns on and a corresponding image signalV_(OUT) that is representative of the magnitude of the charge on thecorresponding charge storage node 54 (e.g., a reset-level or animage-level voltage from one or more photodiodes 34) is produced onoutput path 32. In a typical configuration, there are numerous rows andcolumns of image pixels such as image pixel 22 in image pixel array 20.When row select control signal RS is asserted in a given row, a pathsuch as column line 32 may be used to route signal V_(OUT) from thatimage pixel to per-column control and readout circuit 31 associated withthat column of array 20. If desired, reset-levels and image-levels maybe sampled, held, and converted for each image pixel 22 to allow for kTCreset noise compensation via a correlated double sampling technique, forexample.

Pixels 22 may be provided with gain selection circuitry that enhancesthe dynamic range of the images produced by image sensor 16. Forexample, each pixel 22 may generate a corresponding image signal using aselected gain setting (mode). In some configurations, a selected gainsetting may depend on the amount of light captured by the pixel duringan exposure (i.e., an integration period between resets of the pixelduring which a photosensitive element generates charges in response toincoming light). In other configurations, the gain may be kept at aconstant setting. As shown in FIG. 3, image pixels 22-1 and 22-2 mayinclude capacitors 62 and transistors 64 coupled in series betweenterminals 66 and floating diffusion nodes 54 (e.g., pixel 22-1 mayinclude a first capacitor 62-1 and transistor 64-1 coupled in seriesbetween terminal 66-1 and floating diffusion node 54-1 whereas pixel22-2 may include a second capacitor 62-2 and transistor 64-2 coupled inseries between terminal 66-2 and floating diffusion node 54-2). In onesuitable arrangement, terminals 66 may be coupled to positive powersupply voltage Vaa. In another suitable arrangement, terminals 66 may becoupled to ground power supply Vss.

Transistors 64 may have gate terminals that are controlled using dualconversion gain control signal DCG. Pixels 22-1 and 22-2 may receivedual conversion gain control signals DCG over the corresponding columnline 32B from circuits 31 (e.g., pixel 22-1 may receive dual conversiongain signal DCG over column lines 32-1 from column circuit 31-1 whereaspixel 22-2 may receive dual conversion gain signal DCG over column lines32-2 from column circuit 31-2). Pixel 22 may be operable in a highconversion gain mode (high gain mode) and in a low conversion gain mode(low gain mode). If transistor 64 is disabled (e.g., if signal DCG islow), the corresponding pixel 22 is placed in the high conversion gainmode. If transistor 64 is enabled (e.g., if signal DCG is high), thecorresponding pixel 22 is placed in the low conversion gain mode.

In general, pixel conversion gain is inversely proportional to theamount of loading capacitance at node FD. When transistor 64 is turnedon, capacitor 62 is switched into use in order to provide floatingdiffusion node 54 with additional capacitance (e.g., additional chargestorage capacity). This results in a lower conversion gain for pixel 22.When transistor 64 is turned off, the additional loading of capacitor 66is removed and pixel 22 reverts to a relatively higher pixel conversiongain configuration. Per-column control circuits 31 may independentlyadjust dual conversion gain control signal DCG provided to pixels 22across a selected row while the row select signal RS is asserted for allof the pixels in that row (e.g., control signal DCG may be pulsed highor low without deasserting row select signal RS). In this way,per-column control circuits may individually adjust the conversion gainprovided for each pixel 22 in a given row of array 20 during imagecapture and readout operations.

The example of FIG. 3 is merely illustrative. Each pixel 22 may includeany desired number of photosensitive regions 34 (e.g., one photodiode34, three photodiodes 34, four photodiodes 34, etc.) coupled to acorresponding charge storage node 54 (e.g., via corresponding chargetransfer gates). Gates 50, 64, 52, and nodes 66, 54, and 48 in eachpixel 22 may be coupled together in any desired manner. If desired,multiple DCG gates 64 may be coupled to each storage region 54 forcoupling storage region 54 to multiple additional storage capacitances62 (e.g., to allow for more finely tuned adjustment of the storagecapacity in the pixel). In general, each pixel 22 may include anydesired number of photosensitive regions coupled to a charge storageregion by corresponding charge transfer gates and may include one ormore additional capacitances coupled to the charge storage region by oneor more corresponding DCG gates that are controlled by a correspondingper-column control circuit 31.

If desired, column control logic circuits 31 may read out image signalsfrom pixels 22 and may process the pixels to determine whether the pixelconversion gain needs to be adjusted in that column (e.g., for thatpixel). For example, each per-column control circuit 31 may processimage signals of a corresponding pixel in a selected pixel row (e.g., apixel row to which row select signal RS is asserted) to determinewhether that pixel needs to adjust conversion gain regardless of theconversion gain used by the other pixels in the selected pixel row.

FIG. 4 is a flow chart of illustrative steps that may be performed by agiven per-column control circuit 31 for processing image signalscaptured by a given pixel 22 and for adjusting gain in that pixel 22.The steps of FIG. 4 may, for example, be performed by a per-columncontrol circuit 31 coupled to a given pixel 22 via a correspondingcolumn lines 32A and 32B when the pixel row in which the given pixel 22is located is selected by row control circuitry 26. The steps of FIG. 4may be performed independently for each pixel 22 (using a correspondingpixel control circuit 31) in parallel (e.g., simultaneously orconcurrently) to provide active and independent gain control to eachpixel in the selected row while the row is selected.

At step 110, per-column control circuit 31 may deassert dual conversiongain signal DCG provided to the gate terminal of DCG transistor 64 ofthe corresponding pixel 22 (e.g., control circuit 31 may turn off DCGgate 64). In this way, additional capacitance 62 may be removed fromcharge storage region 54 of pixel 22 so that pixel 22 may capture afirst image signal in a high conversion gain mode (high gain mode). Thefirst image signal may, if desired, include a reset-level signal and animage-level signal for performing a correlated double sampling (CDS)readout operation.

At step 112, per-column control circuit 31 may receive the first imagesignal captured by pixel 22 in the high conversion gain mode (e.g.,while control signal DCG is deasserted). Column control circuit 31 maysample and hold the reset-level and image-level signals on associatedsample and hold circuitry.

At step 114, column control circuit 31 may compare the first imagesignal received from pixel 22 to a selected threshold value to determinewhether additional charge storage is required at pixel 22 (e.g., todetermine whether to adjust the gain or switch gain modes at pixel 22).For example, column control circuit 31 may include analog comparatorcircuitry that compares the analog first image signal to the selected(predetermined) threshold value. In another suitable arrangement, columncontrol circuit 31 may include analog-to-digital converter circuitrythat converts the first image signal into a first digital pixel valueand digital comparison logic that compares the first digital pixel valueto the selected threshold value.

The selected threshold value may be any desired threshold fordetermining whether the gain of pixel 22 needs to be adjusted. As oneexample, the selected threshold value may be a saturation level (orbased on a saturation level) associated with pixel 22. For example, thethreshold value may be set to the 100% of the saturation level ofstorage region 54, to 90% of the saturation level of storage region 54,to 80% of the saturation level of storage region 54, or to any otherdesired value (a value less than or equal to 100% of the saturationlevel, less than or equal to 90% of the saturation level, less than orequal to 80% of the saturation level, etc.). In this scenario, thethreshold value is selected such that the first image signal is comparedto a voltage level at which the charge storage capacity of storageregion 54 in pixel 22 is sufficiently full (e.g., sufficiently saturatedwith charge). When pixel 22 is saturated, it may be desirable to extendthe storage capacity associated with pixel 22 (e.g., adjust the gain ofpixel 22) so that pixel 22 may continue to capture and store charge(e.g., without saturating or blooming). The selected threshold value maybe determined during manufacturing and characterization of imagingsystem 10 and may be stored on imaging system 10 for use during normalimaging operations.

If the comparator circuitry in column circuit 31 determines that thefirst image signal is less than or equal to the selected threshold value(e.g., that the charge storage region on pixel 22 is not saturated or issufficiently below saturation such as when pixel 22 is located withindarker portions 27 of the imaged scene), processing may proceed to step117 as shown by path 116. At step 117, column circuit 31 may set thefirst signal as a final image signal and processing may proceed to step126 to output the final image signal to other circuitry for performingadditional processing (e.g., other image processing circuitry, displaycircuitry, etc.). In this scenario, there may be no need to adjust thegain of pixel 22, as storage node 54 does not saturate with charge.

If the comparator circuitry in column circuit 31 determines that thefirst image signal is greater than the selected threshold value (e.g.,determines that the first image signal saturates charge storage node 54on pixel 22 or is sufficiently close to saturation such as when pixel 22is located within brighter portions 25 of the imaged scene), processingmay proceed to step 120 as shown by path 118.

At step 120, column circuit 31 may assert dual conversion gain signalDCG to the gate terminal of DCG transistor 64. Transistor 64 may beturned on and may extend the storage capacity of storage node 54 toinclude the capacitance of capacitor 62 so that pixel 22 may capture asecond image signal with the low conversion gain (e.g., in the lowconversion gain mode). If desired, the second image signal may include areset-level signal and an image-level signal for performing a CDSreadout operation.

At step 122, column circuit 31 may receive the second image signalcaptured by pixel 22 in the low conversion gain mode (e.g., whilecontrol signal DCG is asserted). Column control circuit 31 may sampleand hold the reset-level and image-level signals on sample and holdcircuitry.

At step 124, column circuit 31 may process the received second signal togenerate a final image signal. If desired, column circuit 31 may modify(adjust) the second signal based on the pixel gain of pixel 22. Forexample, column circuit 31 may generate the final image signal bydividing the second image signal by the pixel gain. The pixel gain ofpixel 22 may be defined herein as the ratio of the conversion gain ofpixel 22 when DCG gate 64 is turned off to the conversion gain of pixel22 when DCG gate 64 is turned on (the pixel gain may, for example, bedetermined during calibration and characterization of image sensor 16during manufacture, testing, or assembly of imaging system 10 of FIG.1). As an example, when the conversion gain of pixel 22 with DCG gate 64turned off is 150 uV/e− and the conversion gain of pixel 22 with DCGgate 64 turned on is 50 uV/e− (e.g., as determined duringcharacterization of image sensor 16 prior to normal operation of imagingsystem 10), the pixel gain of pixel 22 may be equal to 150/50=3.0.Column circuit 31 may thereby generate the final image signal bydividing the second image signal by 3.0.

At step 126, column circuit 31 may output the final image signal toother circuitry for performing additional processing (e.g., other imageprocessing circuitry within readout circuitry 28, within processingcircuitry 18, display circuitry, etc.). In this way, column readoutcircuit 31 may analyze the image signals captured by a correspondingpixel 22 in real time to determine whether the pixel is located in abright portion of the scene (e.g., when the first image signal isgreater than the threshold value) or in a dark portion of the scene(e.g., when the first image signal is less than the threshold value) sothat the gain may be adjusted to suit the brightness of the portion ofthe scene in which the pixel is located (e.g., so that only a highconversion gain mode may be used when the pixel 22 is in a darkerportion of the image and both the high and low conversion gain modes maybe used when pixel 22 is in a brighter portion of the image, therebyallowing for sufficient signal-to-noise ratio without saturation orblooming in the final image signal). By repeating the steps of FIG. 4for each column circuit 31 to readout and adjust gain independently foreach pixel 22 in a corresponding row of array 20, final image signalsmay be readout with an intelligently selected gain setting based onwhether a given pixel is located in a dark or bright portion of theimage across the corresponding pixel row (e.g., thereby allowing forsufficient signal-to-noise ratio in the final image signal generatedacross the corresponding pixel row without generating saturation orblooming regardless of whether different portions of the correspondingpixel row are illuminated by darker or brighter portions of the imagedscene).

If desired, gain control provided by per-column control circuit 31 maybe finely tuned by adjusting the gain provided by column amplifiers 33(as shown in FIG. 2) in addition to adjusting the conversion gain inpixels 22. For example, in addition to adjusting gain by turning DCGgates 64 on or off, a first column circuit such as circuit 31-1 of FIG.3 may adjust a first amplifier 33 on column line 32-1 to have a firstgain value whereas a second column circuit such as circuit 31-2 mayadjust a second amplifier 33 on column line 32-2 to have a second gainvalue based on whether the corresponding pixels 22 are in brighter ordarker portions of the scene (e.g., based on the image signals capturedby the corresponding pixels 22).

FIG. 5 is a flow chart of illustrative steps that may be performed by agiven per-column control circuit 31 for adjusting the gain provided byan associated pixel 22 by adjusting dual conversion gain control signalDCG and/or by adjusting the gain of a corresponding column amplifier 33.The steps of FIG. 5 may, for example, be performed by a per-columncontrol circuit 31 coupled to a given pixel 22 via corresponding columnlines 32A and 32B when the pixel row in which the given pixel 22 islocated is selected by row control circuitry 26. The steps of FIG. 5 maybe performed independently for each pixel 22 (using a correspondingpixel control circuit 31) in parallel (e.g., simultaneously orconcurrently) to provide active and independent gain control to eachpixel in the selected row.

At step 130, per-column pixel control circuit 31 may deassert controlsignal DCG to the corresponding pixel 22 to turn off DCG gate 64.Control circuit 31 provide control signals to the corresponding columnamplifier 33 to set the gain of column amplifier 33 to 1.0 (e.g., sothat the power level of image signals received by amplifier 33 is thesame as the power level of image signals output by amplifier 33).

At step 132, column control circuit 31 may receive the first imagesignal captured by pixel 22 through amplifier 33. For example, columncircuit 31 may receive a first reset-level and image-level signal fromamplifier 33.

At step 134, column circuit 31 may compare the first image signal to aselected threshold value to determine whether the first image signal isgreater than or less than the selected threshold value (e.g., todetermine whether pixel 22 is saturating or sufficiently close tosaturating storage node 54). If the first image signal is less than orequal to the selected threshold value, processing may proceed to step138 as shown by path 136.

At step 138, column circuit 31 may adjust the gain of amplifier 33 basedon the threshold value (e.g., the maximum pixel value immediately beforestorage node 54 saturates) and/or the first image signal (e.g., themagnitude of the first image signal). For example, column circuit 31 mayprovide control signals to amplifier 33 that set the gain of amplifier33 to the ratio of the selected threshold value to the magnitude of thefirst image signal. In this way, the gain of amplifier 33 may beincreased to ensure that the charge capacity of charge storage region 54is fully utilized without saturating (e.g., to ensure that the finalimage signals have a maximum signal-to-noise ratio). Image pixel 22 maycapture a second image signal and may provide the second image signal toamplifier 33. Amplifier 33 may amplify the second image signal based onthe selected amplifier gain.

At step 140, column circuit 31 may receive the amplified second imagesignal from an output of amplifier 33. The amplified second image signalmay include a second reset-level signal and an image-level signal.Processing may subsequently proceed to step 148.

At step 148, column circuit 31 may modify the second image signal basedon the pixel gain of pixel 22 and the amplifier gain of amplifier 33(e.g., the amplifier gain as set while processing step 138) to generatea final image signal. For example, circuit 31 may generate the finalimage signal by dividing the second image signal by the pixel gain andthe selected amplifier gain. Processing may subsequently proceed to step150 to output the final image signals to external processing circuitry.

If the first image signal is greater than the selected threshold value(e.g., if storage node 54 is saturated or sufficiently close tosaturation), processing may proceed to step 144 as shown by path 142. Atstep 144, column circuit 31 may assert dual conversion gain signal DCGto the gate terminal of DCG transistor 64 to turn on transistor 64(e.g., to extend the storage capacity of storage node 54 to include thecapacitance of capacitor 62 so that pixel 22 may capture a second imagesignal with the low conversion gain).

At step 146, column circuit 31 may receive the second image signal fromthe output of amplifier 33. The second image signal received from theoutput of amplifier 33 may have the same power level as the second imagesignal when received at the input of amplifier 33 (e.g., because thegain of amplifier 33 is set to 1.0 while processing step 130). Ifdesired, the second image signal may include a reset-level signal and animage-level signal for performing a CDS readout operation.

At step 148, column circuit 31 may modify the second image signal basedon the pixel gain of pixel 22 and the amplifier gain of amplifier 33(e.g., as set while processing step 138) to generate a final imagesignal. For example, circuit 31 may generate the final image signal bydividing the second image signal by the pixel gain and the selectedamplifier gain (e.g., 1.0). Processing may subsequently proceed to step150 to output the final image signals to external processing circuitry.

By controlling both the gain of amplifier 33 and the conversion gain ofpixel 22, column circuit 31 may more finely tune the gain of pixel 22relative to scenarios when only the conversion gain of pixel 22 isadjusted. The steps of FIG. 5 may be performed for each column circuit31 to readout and adjust the gain independently for each pixel 22 in aselected row of array 20 and final image signals may be readout with anintelligently selected gain setting based on whether a given pixel islocated in a dark or bright portion of the image across thecorresponding pixel row (e.g., thereby allowing for sufficientsignal-to-noise ratio in the final image signal generated across thecorresponding pixel row without generating saturation or bloomingregardless of whether different portions of the corresponding pixel roware illuminated by darker or brighter portions of the imaged scene).

The example of FIGS. 4 and 5 is merely illustrative. If desired, columncircuit 31 may compare the first image signal to any desired number ofthreshold values. For example, column circuit 31 may compare the firstimage signal to multiple threshold values each corresponding to anassociated dual conversion gain gate 64 in pixel 22 (e.g., in scenarioswhere multiple dual conversion gain gates 64 are coupled between chargestorage region 54 and respective capacitances 62) and may selectivelyturn on one or more of the DCG gates 64 to adjust the storage capacity(and conversion gain) of pixel 22 based on the image signals that arecaptured by pixel 22.

By allowing active, per-pixel adjustment of gain provided for pixels 20in a given row of array 20, column circuits 31 may improve theintra-scene dynamic range of the final image (e.g., so that brighterportions of the image are not over-saturated while darker portions ofthe same image have sufficient signal-to-noise ratio). If desired,imaging system 10 may be operated in a linear mode or in ahigh-dynamic-range mode (HDR mode) in which long and short exposurepixel values are captured and combined to provide an image with improveddynamic range. The dynamic range of an image may be defined herein asthe ratio of the brightest portion of an image to the darkest portion ofan image. As an example, the intra-scene dynamic range (e.g., thedynamic range within a given image) of the captured image may beimproved from 64 dB to 78 dB in a linear imaging mode and from 88 dB to100 dB in an HDR imaging mode when performing per-pixel gain adjustmentsas described in connection with FIGS. 1-5 relative to scenarios where asingle common gain adjustment is performed for all pixels across a rowof pixels.

FIG. 6 is an illustrative timing diagram showing how row and columncontrol signals may be provided to array 20 when performing per-pixelgain adjustments. As shown in FIG. 6, control signals such as row selectcontrol signal RS, reset control signal RST, and charge transfer signalTX may be provided to a given row of pixels from row control circuitry28 over row control lines 30. Dual conversion gain control signal DCGmay be provided to given pixel 22 in the given row by per-column controlcircuit 31. Sample and hold control signals SHR and SHS may be providedto control circuit 31 for performing sample and hold operations on imagesignals received from pixel 22. Current source control signal VLN_enablemay be provided to a current source coupled to the corresponding columnline 32A.

At time T1, row control circuitry 26 and control circuitry 31 may assertreset control signal RST to turn on reset gate 50 and assert controlsignal DCG to turn on gate 64 of pixel 22 (and each of the other pixelsin the same row of array 20 as pixel 22). Reset gate 50 may be turnedoff by deasserting reset control signal RST and gate 64 may be turnedoff by deasserting control signal DCG at time T2.

At time T3, row select control signal RS may be asserted to thecorresponding row of pixels in which pixel 22 is located to select thatrow of pixels and to enable reading out of image signals from that row(e.g., by turning on row select transistors 56). Sample and hold resetsignal SHR may be asserted at time T3 to sample a reset-level signalfrom pixel 22 onto control circuit 31. Current source control signalVLN_enable may be asserted at time T3 to enable a current source coupledto column line 32A.

At time T4, sample and hold reset signal SHR may be deasserted. At timeT5, row control circuitry 26 may assert charge transfer control signalTX to enable charge transfer gate 52 on pixel 22 to transfer chargegenerated by photodiode 34 on pixel 22 onto charge storage region 54. Attime T6, charge transfer signal TX may be deasserted.

At time T7, sample and hold image signal SHS may be asserted to samplean image level signal from pixel 22 onto control circuit 31. The imagelevel signal and reset level signal may be used for performing CDSreadout operations on the image signals. As an example, steps 110-112 ofFIG. 4 and steps 130 and 132 of FIG. 5 may be performed between times T1and T6 of FIG. 6 (sometimes referred to herein as a phase one readoutoperation).

At time T8, control circuit 31 may process the read out image signal(e.g., the signals read out between times T3 and T8) to determinewhether excessive charge has been stored on storage node 54 (e.g., bycomparing the read out image signal to the predetermined threshold atstep 134 of FIG. 5 or step 114 of FIG. 4). Other control circuits 31 incircuitry 28 may process the image signals read out from correspondingpixels in the selected row of array 28 in parallel. In the scenario ofFIG. 5, if control circuit 31 determines that the read out image signalhas a magnitude that is less than or equal to the threshold value,control circuit 31 may increase the gain of amplifier 33 and may assertthe shaded control signals shown between times T8 and T13 of FIG. 6without asserting control signal DCG (e.g., while processing steps 138,140, 148, and 150 of FIG. 5) to read out second image signals. In thescenario of FIG. 4, if control circuit 31 determines that the read outimage signal has a magnitude that is less than or equal to the threshold(e.g., that there is not excessive charge stored on storage node 54),control circuit 31 may omit the shaded control signals shown betweentimes T8 and T13 of FIG. 6 and the read out image signals may be used asfinal image signals that are output to additional processing circuitry.The time period between times T8 and T13 as shown in FIG. 6 maysometimes be referred to herein as a phase two readout operation.

If control circuit 31 determines that the read out image signal isgreater than the threshold value (e.g., that there is excessive chargestored on storage node 54), control circuit 31 may adjust the conversiongain of pixel 22 (e.g., by performing step 144 of FIG. 5 or step 120 ofFIG. 4) without deasserting row control signal RS using row controlcircuitry 26. For example, at time T9, control circuit 31 may assertdual gain conversion control signal DCG to turn on DCG gate 64 in pixel22 while row select gate 56 in pixel 22 remains turned on (e.g., withoutturning off the row select gate 56 of that pixel). In other words, DCGgates 64 may be independently turned on for some or all of the pixels inthe selected row without selecting a different row of array 20 forcapturing image signals (e.g., image signals in a given pixel of aselected row may capture image signals with its DCG gate 64 turned onand with its DCG gate 64 turned off while the selected row is enabledwhile another pixel in the selected row only captures image signals withits DCG gate 64 turned off).

At time T10, transfer control signal TX may be asserted to transferadditional charge generated by photodiode 34 onto storage node 54 (andcapacitor 62). At time T11, control signal TX may be deasserted andsample and hold image control signal SHS may be asserted to readout thetransferred charge as the second image signal from pixel 22.

At time T12, control signals SHS, RS, and DCG may be deasserted. Aftertime T13, control circuits 31 may perform a readout process such as arolling shutter or a global shutter readout process to readout the finalimage signals. Current source control signal VLN_enable may be disabledat time T13. The example of FIG. 6 is merely illustrative. If desired,the control signals may be asserted and deasserted in any desired order.

In this way, dual conversion gain gate 64 in a given pixel 22 may beselectively turned on only if column control circuit 31 determines thatthat pixel 22 requires additional storage capacity (e.g., based on theimage signals captured by that pixel between times T1 and T8) prior toperforming image capture and readout operations on subsequent rows inthe array. Dual conversion gain gate 64 may only be turned on in pixels22 of a given row if those pixels are capturing excessive charge (e.g.,due to those pixels being located in brighter portions of the imagedscene for which the captured first signals exceed the threshold level),while pixels 22 of the given row that do not capture excessive charge(e.g., pixels in darker portions of the imaged scene for which thecaptured first signals did not exceed the threshold level) are read outwithout turning on the corresponding dual conversion gain gate 64.

FIG. 7 shows in simplified form a typical processor system 300, such asa digital camera, which includes an imaging device 200 (e.g., an imagingdevice 200 such as device 10 of FIGS. 1-6 and the techniques forcapturing images using per-column pixel gain adjustments). The processorsystem 300 is exemplary of a system having digital circuits that couldinclude imaging device 200. Without being limiting, such a system couldinclude a computer system, still or video camera system, scanner,machine vision, vehicle navigation, video phone, surveillance system,auto focus system, star tracker system, motion detection system, imagestabilization system, and other systems employing an imaging device.

The processor system 300 generally includes a lens 396 for focusing animage on pixel array 20 of device 200 when a shutter release button 397is pressed, central processing unit (CPU) 395, such as a microprocessorwhich controls camera and one or more image flow functions, whichcommunicates with one or more input/output (I/O) devices 391 over a bus393. Imaging device 200 also communicates with the CPU 395 over bus 393.The system 300 also includes random access memory (RAM) 392 and caninclude removable memory 394, such as flash memory, which alsocommunicates with CPU 395 over the bus 393. Imaging device 200 may becombined with the CPU, with or without memory storage on a singleintegrated circuit or on a different chip. Although bus 393 isillustrated as a single bus, it may be one or more busses or bridges orother communication paths used to interconnect the system components.

Various embodiments have been described illustrating systems and methodsfor generating images using an image sensor pixel array having per-pixelgain adjustment capabilities.

An imaging system may include an array of image sensor pixels arrangedin rows and columns, row control circuitry coupled to the array viamultiple row control lines, and readout circuitry coupled to the arrayvia multiple column lines. The array may include any desired number ofimage pixels. For example, the array may include first and second imagepixels located in two different columns of the array and in a common rowof the array. The row control circuitry may assert a row select signalprovided to the common row of the array over a corresponding row controlline (e.g., to select the pixels in that row for capturing and readingout image signals).

The readout circuitry may include multiple column readout circuits eachcoupled to a corresponding column of the array. A first column readoutcircuit may control the first image pixel so that the first image pixelexhibits a first gain while the row control circuitry (continuously)asserts the row select signal to the common row. A second column readoutcircuit may control the second image pixel so that the second sensorpixel exhibits a second gain that is different from the first gain whilethe row control circuitry (continuously) asserts the row select signal.For example, the first and second column readout circuits mayselectively activate (e.g., selectively turn on and/or off) dualconversion gain gates in the first and second image pixels so that thefirst and second image pixels exhibit the first and second gains (e.g.,first and second conversion gains). Column readout amplifiers may beinterposed on each column line. If desired, the first column readoutcircuit may control a first column readout amplifier coupled to thefirst image pixel so that the first column readout amplifier exhibits afirst desired amplifier gain. The second column readout circuit maycontrol a second column readout amplifier coupled to the second imagepixel so that the second column readout amplifier exhibits a seconddesired amplifier gain.

If desired, the first and second column readout circuits may determinewhether to adjust the pixel gain of the respective first and secondimage pixels based on image signals that are captured by the first andsecond image pixels. For example, the first readout circuit may turn offa dual conversion gain transistor in the first image pixel and mayreceive a first image signal from the first image pixel while the dualconversion gain transistor is turned off. The first column readoutcircuit may compare the received first image signal to a predeterminedthreshold value and may turn on the dual conversion gain transistor inthe first image pixel in response to determining that the first imagesignal has a magnitude that is greater than the predetermined thresholdvalue. The first column readout circuit may receive a second imagesignal from the first image pixel while the dual conversion gaintransistor is turned on and may generate a final image signal bymodifying the second image signal by a pixel gain value associated withthe first image pixel. The first column readout circuit may output thefinal image signal to additional image processing circuitry. If desired,the first column readout circuit may output the first image signal toadditional image processing circuitry in response to determining thatthe first image signal has a magnitude that is less than thepredetermined threshold value (e.g., without receiving any image signalswhile the dual conversion gain transistor is turned on). This processmay be independently performed by the second column readout circuit andthe second image pixel. In this way, gain may be independently analyzedand adjusted for image pixels across a given row of the array while thegiven row is selected using independent column readout and controlcircuits.

If desired, the imaging system may further include a central processingunit, memory, input-output circuitry, and a lens that focuses light ontothe array of image sensor pixels.

The foregoing is merely illustrative of the principles of this inventionand various modifications can be made by those skilled in the artwithout departing from the scope and spirit of the invention. Theforegoing embodiments may be implemented individually or in anycombination.

What is claimed is:
 1. A method of operating an imaging system having anarray of image sensor pixels arranged in rows and columns, row controlcircuitry coupled to the array via a plurality of row lines, and readoutcircuitry coupled to the array via a plurality of column lines, whereinthe array comprises first and second image sensor pixels in a given rowof the array, the method comprising: with the row control circuitry,asserting a row select signal provided to the given row of the arrayover a corresponding one of the plurality of row lines; with the readoutcircuitry, controlling the first image sensor pixel so that the firstimage sensor pixel exhibits a first gain while the row control circuitryasserts the row select signal; and with the readout circuitry,controlling the second image sensor pixel so that the second imagesensor pixel exhibits a second gain that is different from the firstgain while the row control circuitry asserts the row select signal. 2.The method defined in claim 1, wherein controlling the first imagesensor pixel so that the first image sensor pixel exhibits the firstgain comprises: providing a first gain control signal to the first imagesensor pixel over a first column line of the plurality of column lines.3. The method defined in claim 2, wherein controlling the second imagesensor pixel so that the second image sensor pixel exhibits the secondgain comprises: providing a second gain control signal to the secondimage sensor pixel over a second column line of the plurality of columnlines that is different from the first column line.
 4. The methoddefined in claim 3, wherein the first image sensor pixel comprises acharge storage region and a capacitor coupled to the charge storageregion via a dual conversion gain gate, wherein providing the first gaincontrol signal to the first image sensor pixel comprises: providing afirst dual conversion gain control signal to the dual conversion gaingate to turn off the dual conversion gain gate.
 5. The method defined inclaim 4, wherein the second image sensor pixel comprises an additionalcharge storage region and an additional capacitor coupled to theadditional charge storage region via an additional dual conversion gaingate, wherein providing the second gain control signal to the secondimage sensor pixel comprises: providing a second dual conversion gaincontrol signal to the additional dual conversion gain gate to turn onthe second dual conversion gain gate while the first dual conversiongain gate is turned off.
 6. The method defined in claim 3, wherein thefirst image sensor pixel comprises a charge storage region, a pluralityof capacitors, and a plurality of dual conversion gain gates, whereineach capacitor of the plurality of capacitors is coupled to the chargestorage region via a respective dual conversion gain gate of theplurality of dual conversion gain gates, and wherein providing the firstgain control signal to the first image sensor pixel comprises: providingdual conversion gain control signals to each of the dual conversion gaingates of the plurality of dual conversion gain gates to turn off thedual conversion gain gates.
 7. The method defined in claim 1, whereinthe readout circuitry is coupled to the first image sensor pixel by afirst column line of the plurality of column lines, wherein the readoutcircuitry is coupled to the second image sensor pixel by a second columnline of the plurality of column lines, wherein a first readout amplifiercircuit is interposed on the first column line, and wherein a secondreadout amplifier circuit is interposed on the second column line, themethod further comprising: with the readout circuitry, instructing thereadout amplifier circuit to exhibit a first amplifier gain; and withthe readout circuitry, instructing the readout amplifier circuit toexhibit a second amplifier gain that is different from the firstamplifier gain.
 8. The method defined in claim 1, further comprising:with the readout circuitry, turning off a dual conversion gaintransistor in the first image sensor pixel; and with the readoutcircuitry, receiving a first image signal from the first image sensorpixel while the dual conversion gain transistor is turned off.
 9. Themethod defined in claim 8, further comprising: with the readoutcircuitry, comparing the first image signal to a predetermined thresholdvalue; and with the readout circuitry, turning on the dual conversiongain transistor in the first image sensor pixel in response todetermining that the first image signal has a magnitude that is greaterthan the predetermined threshold value.
 10. The method defined in claim9, further comprising: with the readout circuitry, outputting the firstimage signal to image processing circuitry in response to determiningthat the first image signal has a magnitude that is less than thepredetermined threshold value.
 11. The method defined in claim 9,further comprising: with the readout circuitry, receiving a second imagesignal from the first image sensor pixel while the dual conversion gaintransistor is turned on; with the readout circuitry, generating a finalimage signal by modifying the second image signal based on a pixel gainvalue associated with the first image sensor pixel; and with the readoutcircuitry, outputting the final image signal to image processingcircuitry, wherein the pixel gain value comprises a ratio of aconversion gain of the first image sensor pixel while the dualconversion gain transistor is turned off to a conversion gain of thefirst image sensor pixel while the dual conversion gain transistor isturned on and wherein modifying the second image signal based on thepixel gain value comprises: dividing the second image signal by thepixel gain value.
 12. An imaging system, comprising: an array of imagesensor pixels arranged in rows and columns, wherein the array comprisesa first image sensor pixel having a first dual conversion gain gatecoupled to a first charge storage node and a second image sensor pixelhaving a second dual conversion gain gate coupled to a second chargestorage node; a first column control circuit coupled to a first columnof the array, wherein the first image sensor pixel is located in thefirst column and the first column control circuit is configured toselectively activate the first dual conversion gain gate in the firstimage sensor pixel; and a second column control circuit that isdifferent from the first column control circuit, wherein the secondcolumn control circuit is coupled to a second column of the array,wherein the second image sensor pixel is located in the second column,and wherein the second column control circuit is configured toselectively activate the second dual conversion gain gate in the secondimage sensor pixel.
 13. The imaging system defined in claim 12, whereinthe first column control circuit is coupled to the first column via afirst column line, wherein the second column control circuit is coupledto the second column via a second column line, further comprising: rowcontrol circuitry coupled to the array via a plurality of row controllines, wherein the row control circuitry is configured to provide rowcontrol signals to the image sensor pixels in the array over theplurality of row control lines.
 14. The imaging system defined in claim13, wherein the first and second image sensor pixels are located in agiven row of the array that is coupled to the row control circuitry by agiven row control line of the plurality of row control lines and whereinthe row control circuitry is configured to provide row select controlsignals to the first and second image sensor pixels over the given rowcontrol line.
 15. The imaging system defined in claim 14, wherein thefirst charge storage node of the first image sensor pixel is coupled tothe first column line by a first row select gate, wherein the secondcharge storage node of the second image sensor pixel is coupled to thesecond column line by a second row select gate, wherein the row controlcircuitry is configured to turn on the first and second row select gatesby concurrently providing the row select control signals to the firstand second row select gates, wherein the first column control circuit isconfigured to selectively activate the first dual conversion gain gatein the first image sensor pixel while the first row select gate isturned on, and wherein the second column control circuit is configuredto selectively activate the second dual conversion gain gate in thesecond image sensor pixel while the second row select gate is turned on.16. The imaging system defined in claim 12, wherein the first columncontrol circuit is configured to readout a first image signal from thefirst image sensor pixel while the first dual conversion gain gate isdeactivated and is wherein the first column control circuit isconfigured to selectively activate the first dual conversion gain gatebased on the first image signal.
 17. The imaging system defined in claim16, wherein the first column control circuit comprises: comparatorcircuitry, wherein the comparator circuitry is configured to compare thefirst image signal to a selected threshold level.
 18. The imaging systemdefined in claim 17, wherein the first column control circuit isconfigured to activate the first dual conversion gain gate in responseto determining that the first image signal has a magnitude that exceedsthe selected threshold level, wherein the first column control circuitis configured to readout a second image signal from the first imagesensor pixel while the first dual conversion gain gate is activated,wherein the second column control circuit is configured to read out athird image signal from the second image sensor pixel while the seconddual conversion gain gate is deactivated, wherein the second columncontrol circuit comprises additional comparator circuitry configured tocompare the third image signal to an additional selected thresholdlevel, wherein the second column control circuit is configured toactivate the second dual conversion gain gate in response to determiningthat the third image signal exceeds the additional selected threshold,and wherein the second column control circuit is configured to readout afourth image signal from the second image sensor pixel while the seconddual conversion gain gate is activated.
 19. The imaging system definedin claim 12, further comprising: a first capacitor coupled to the firstcharge storage node via the first dual conversion gain gate; and asecond capacitor coupled to the first charge storage node via a seconddual conversion gate that is different from the first dual conversiongain gate.
 20. A system, comprising: a central processing unit; memory;input-output circuitry; and an imaging device, wherein the imagingdevice comprises: an array of image sensor pixels arranged in rows andcolumns, wherein the array comprises a first image sensor pixel locatedin a first column and a given row of the array and a second image sensorpixel located in a second column and the given row of the array; rowcontrol circuitry coupled to the given row of the array via a rowcontrol line; a first readout circuit coupled to the first column of thearray via a first column line; and a second readout circuit coupled tothe second column of the array via a second column line, wherein, whilethe row control circuitry continuously activates the given row of thearray, the first readout circuit is configured to selectively activate afirst dual conversion gain gate of the first image sensor pixel using afirst control signal based on a first image signal captured by the firstimage sensor pixel while the first dual conversion gain gate isdeactivated, and the second readout circuit is configured to selectivelyactivate a second dual conversion gain gate of the second image sensorpixel using a second control signal based on a second image signalcaptured by the second image sensor pixel while the second dualconversion gain gate is deactivated.